The present disclosure relates to semiconductor device fabrication, and, more specifically, to methods of forming semiconductor devices using overlay marks in forming and patterning stacked material layers used for fabricating structural features.
Fabrication of integrated circuits generally requires the formation of multiple integrated circuit patterns on one or more layers over a substrate wafer. These patterns generally include numerous regions of micro-structures or nano-structures that are formed through photolithography. Photolithography is a commonly used technique in the manufacture of semiconductor devices. The process uses patterns to define regions on a substrate. More specifically, with photolithography, a photoresist layer may be formed on a substrate, such as a silicon wafer, and then the resist layer is covered with a mask containing a pattern. The mask is exposed to radiation, such as ultraviolet light (UV), which is transmitted through transparent areas of the mask to cause a chemical reaction in corresponding regions of the photoresist. In other words, in the course of processing integrated circuits and the like in semiconductor devices, a standard sequence may involve putting down a layer of material, depositing a layer of photoresist on the layer of material, patterning the photoresist by projecting a pattern on it, and developing the resist to produce a pattern of open areas that expose the underlying material, with the other areas of the material still covered by the resist. Depending on whether a positive or negative tone resist is used, the exposed or unexposed portions of the photoresist layer are removed. The portions not protected by the photoresist are then etched to form the features in the substrate.
The relative positioning and alignment, or “overlay,” between such fields is an important component of ensuring the functionality of the resultant integrated circuit, and as such minimizing overlay errors is a significant concern in the manufacturing of the structures of the integrated circuits. Overlay metrology is one way to monitor overlay alignment and minimize overlay errors. To facilitate alignment, overlay marks are formed on the wafer and reticle. This process generally forms alignment marks, referred to herein as overlay marks, in the same layer as the functional circuit structure fields that correspond to the overlay marks. The overlay marks may include different patterns that may then be scanned and/or imaged by an overlay metrology tool. The overlay marks generate a diffraction pattern when scanned by an alignment source from an alignment system. The metrology patterns of any two fields or layers can be measured and compared to determine their relative positions, with deviations in the overlay of the target patterns generally corresponding to deviations in the overlay between the circuit structure fields. Many different types of overlay metrology patterns have been developed to improve the accuracy of overlay metrology measurements.
Advancing technology continues to make smaller structures in integrated circuit (IC) devices. The complexity of advancing technology processes has put a heavy burden on lithography control parameters such as overlay for multiple layers. Advances in overlay target design and metrology has enabled significant improvement in overlay precision and accuracy, but still shows limitation. As structures are being created in the nano-scale size, lithography processes may be unable to maintain overlay requirements due to film stack complexity, weak contrast signals from the overlay marks due to nontransparent films, and/or imbalance of the contrast signals from the overlay marks. Having an overlay out of specification may result in open circuits or shorts in the structures, which not only impacts wafer/die yield but also impacts process throughput due to the necessity to rework the device.